The invention relates to an electroluminescent image display panel with a memory effect, to a device comprising this panel and to a method of driving this panel in order to display images.
Electroluminescent panels comprising an array of electroluminescent cells placed on a semiconductor substrate, for example based on polycrystalline silicon, are known; such panels are generally active-matrix panels.
Electroluminescent panels called “bistable” or “memory effect” panels are known in which each electroluminescent cell:                may be switched from a stable OFF state to a stable ON state in response to a selective activation voltage address signal, or vice versa in response to an erase voltage address signal; and        may be maintained in the OFF or ON state in which it has been placed by this address signal, by applying a voltage called a sustain voltage, which is identical to all the cells of the panel.        
Documents U.S. Pat. No. 4,035,774—IBM , U.S. Pat. No. 4,808,880—CENT and U.S. Pat. No. 6,188,175 B1—CDT disclose panels of this type, in which each cell includes an organic electroluminescent layer and a photoconducting layer that are stacked and connected in series.
Document FR 2 037 158 describes a panel of this type, in which each cell includes a light-emitting diode and a p-n-p-n junction that are connected in series. The drawback of the panel disclosed in that document is that it has to be driven by means of three arrays of electrodes; this is because the devices described in FIGS. 3 and 4 of that document comprise:                an array of common electrodes that connects one of the terminals of each light-emitting diode to the terminals (positive terminals) of the generators 20 and 21 (FIG. 3) or 51 and 54 (FIG. 4);        an array of electrodes serving only for addressing (i.e. the switching of the state of the p-n-p-n junctions) that connects one of the terminals of each p-n-p-n junction directly to the selection means 23 or 53;        an array of electrodes serving only for sustaining (i.e. the supply of the cells after addressing) that connects the same terminal of each p-n-p-n junction to the selection means 23 or 53, via a charge limitation resistor.        
The panels described in document FR 2 037 158 therefore comprise three arrays of electrodes.